1. Introduction to microelectronics to nanoelectronics : design and technology /: design and technology. (2020) Authors: Majumder, Manoj Kumar; Kumbhare, Vijay Rao; Japa, Aditya; Kaushik, Brajesh Kumar Record Type: Book Extent: 1 online resource, illustrations (black and white) View Content: Available online (eLD content is only available in our Reading Rooms) ↗
2. Low area overhead DPA countermeasure exploiting tunnel transistor‐based random number generator. Issue 5 (20th July 2020) Authors: Japa, Aditya; Kumar Majumder, Manoj; Sahoo, Subhendu K.; Vaddi, Ramesh Journal: IET circuits, devices & systems Issue: Volume 14:Issue 5(2020) Page Start: 640 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
3. Negative capacitance FET based energy efficient and DPA attack resilient ultra-light weight block cipher design. (March 2023) Authors: Bheemana, Renuka Chowdary; Japa, Aditya; Yellampalli, Siva sankar; Vaddi, Ramesh Journal: Microelectronics journal Issue: Volume 133(2023) Page Start: Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
4. Negative capacitance FETs for energy efficient and hardware secure logic designs. (January 2022) Authors: Bheemana, Renuka Chowdary; Japa, Aditya; Yellampalli, Siva Sankar; Vaddi, Ramesh Journal: Microelectronics journal Issue: Volume 119(2021) Page Start: Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
5. Reliability enhancement of a steep slope tunnel transistor based ring oscillator designs with circuit interaction. Issue 6 (1st November 2016) Authors: Japa, Aditya; Vallabhaneni, Harshita; Vaddi, Ramesh Journal: IET circuits, devices & systems Issue: Volume 10:Issue 6(2016) Page Start: 522 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
6. Tunnel FET ambipolarity‐based energy efficient and robust true random number generator against reverse engineering attacks. Issue 5 (1st July 2019) Authors: Japa, Aditya; Majumder, Manoj Kumar; Sahoo, Subhendu K.; Vaddi, Ramesh Journal: IET circuits, devices & systems Issue: Volume 13:Issue 5(2019) Page Start: 689 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
7. Tunnel FET‐based ultralow‐power and hardware‐secure circuit design considering p‐i‐n forward leakage. (20th January 2020) Authors: Japa, Aditya; Majumder, Manoj Kumar; Sahoo, Subhendu K.; Vaddi, Ramesh Journal: International journal of circuit theory and applications Issue: Volume 48:Number 4(2020) Page Start: 524 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
8. Tunnel FET‐based ultra‐lightweight reconfigurable TRNG and PUF design for resource‐constrained internet of things. (21st April 2021) Authors: Japa, Aditya; Majumder, Manoj Kumar; Sahoo, Subhendu K.; Vaddi, Ramesh Journal: International journal of circuit theory and applications Issue: Volume 49:Number 8(2021) Page Start: 2299 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗