Introduction to microelectronics to nanoelectronics : design and technology /: design and technology. (2020)

• Record Type: Book
• Further Information: Note: Manoj Kumar Majumder, Vijay Rao Kumbhare, Aditya Japa, Brajesh Kumar Kaushik.
• Authors: Majumder, Manoj Kumar; Kumbhare, Vijay Rao; Japa, Aditya; Kaushik, Brajesh Kumar
• Contents: Chapter 1 SEMICONDUCTOR PHYSICS AND DEVICES; 1.1 Introduction; 1.1.1 Conduction in Solids; 1.1.2 Conductors, Semiconductors, and Insulator; 1.1.3 P-Type and N-Type Semiconductors; 1.1.4 Semiconductor Conductivity; 1.2 Diodes; 1.2.1 Diode Structure and Characteristics; 1.2.2 PN Diode Structure; 1.2.3 Zener Diode Structure; 1.2.4 Diode Applications; 1.3 Bipolar Junction Transistors; 1.3.1 Symbol and Physical Structure; 1.3.2 BJT Configuration; 1.3.3 Second Order Effects; 1.4 Field Effect Transistors; 1.4.1 Junction Field Effect Transistors (JFET); 1.4.2 Metal Oxide Semiconductor Field Effect Transistor (MOSFET); 1.4.3 Advantages of MOSFET over JFET; 1.5 Emerging Devices beyond MOS; 1.5.1 Issues with CMOS Technology Scaling; 1.5.2 Emerging Nano-scale Device Technologies; 1.6 Summary; 1.7 Multiple Choice Questions; 1.8 Short Answer Questions; 1.9 Long Answer Questions; 1.10 References CHAPTER 2 VLSI SCALING AND FABRICATION; 2.1 Introduction to VLSI Scaling; 2.1.1 History and Introduction of VLSI Technology; 2.1.2 VLSI Design’s Concept; 2.1.3 Moore’s Law; 2.1.4 Scale of Integration; 2.1.5 Types of VLSI Chips ( Analog & Digital); 2.1.6 Layout, and Micron & Lambda Rules; 2.2 VLSI Fabrication Process; 2.2.1 Purification, Crystal Growth, and Wafer Processing (CZ and FZ Process); 2.2.2 Oxidation; 2.2.3 Epitaxial Deposition; 2.2.4 Lithography; 2.2.5 Polysilicon and Dielectric Deposition; 2.2.6 Diffusion; 2.2.7 Ion Implementation; 2.2.8 Metallization; 2.2.9 Etching Process; 2.3 Basic CMOS Technology; 2.3.1 N-Well and P-Well CMOS Process; 2.3.2 Twin Tub Process; 2.4 Summary; 2.5 Multiple Choice Questions; 2.6 Short Answer Questions; 2.7 Long Answer Questions; 2.8 References CHAPTER 3 MOSFET MODELING; 3.1 Introduction to MOS Transistor; 3.1.1 Characteristics of MOS Transistor; 3.1.2 Hot Carrier Effects; 3.1.3 Parasitics of MOSFET; 3.1.4 MOSFET Circuit Models; 3.2 MOS Capacitor; 3.2.1 MOS Capacitor with Zero and Nonzero Bias; 3.2.2 Capacitance-Voltage Curves; 3.2.3 Anomalous Capacitance-Voltage Curves; 3.3 MOSFET DC and Dynamic Models; 3.3.1 Pao-Sah Model; 3.3.2 Charge Sheet Model; 3.3.3 Piece-Wise Model for Enhancement Devices; 3.3.4 Small Geometry Model; 3.3.5 Intrinsic Charge and Capacitance; 3.3.6 Meyer Model; 3.4 MOSFET Modeling using SPICE; 3.4.1 Basic Concepts of Modeling; 3.4.2 Model Equations; 3.4.3 Examples using HSPICE; 3.5 Summary; 3.6 Multiple Choice Questions; 3.7 Short Answer Questions; 3.8 Long Answer Questions; 3.9 References CHAPTER 4 COMBINATIONAL AND SEQUENTIAL DESIGN IN CMOS; 4.1 CMOS Inverter; 4.1.1 Design; 4.1.2 Operation; 4.1.3 Transient and VTC Characteritsitics; 4.1.4 Significance of CMOS Inverter; 4.2 Static Behavior of Inverter; 4.2.1 Switching Threshold; 4.2.2 Noise Margin; 4.2.3 Robustness of CMOS inverter by scaling supply voltage; 4.3 Dynamic behavior of CMOS inverter; 4.3.1 Capacitances; 4.3.2 Power and Energy consumption; 4.4 Design of Combinational Logic Design; 4.4.1 Complementary CMOS logic; 4.4.2 Ratioed Logic; 4.4.3 Pass-Transistor Logi; 4.5 CMOS Sequential Design; 4.5.1 Introduction; 4.5.2 Metrics for CMOS Sequential Design; 4.6 Static Latches and Registers; 4.6.1 The Bistability Principle; 4.6.2 SR Flip-Flops; 4.6.3 D-latches and Flip-Flops; 4.6.4 Master slave Flip-flop; 4.7 Summary; 4.8 Multiple Choice Questions; 4.9 Short Questions; 4.10 Long Questions; 4.11 References ; CHAPTER 5 ANALOG CIRCUIT DESIGN; 5.1 Introduction to Analog Design; 5.2 MOS device from Analog perspective; 5.2.1 I/V Characteristics; 5.2.2 Second-order Effects; 5.2.3 MOS Small Signal Model; 5.3 Single Stage Amplifier; 5.3.1 Common Source; 5.3.2 Common Gate; 5.3.3 Source Follower; 5.4 Current mirrors; 5.4.1 Introduction; 5.4.2 Basic Current Mirror; 5.4.3 Cascode current Mirror; 5.5 Differential Amplifiers; 5.5.1 Single ended and differential Operation; 5.5.2 Basic Differential Pair; 5.5.3 Differential Pair with MOS load; 5.6 Operational Amplifiers; 5.6.1 Fundamentals and General Op-amp metrics; 5.6.2 Two Stage Op-amp; 5.7 Digital-to-Analog and Analog-to-Digital Converters; 5.7.1 Introduction; 5.7.2 Types of Digital-to-Analog Converters; 5.7.3 Types of Analog-to-Digital Converters; 5.8 Summary; 5.9 Multiple Choice Questions; 5.10 Short Answer Questions; 5.11 Long Answer Questions; 5.12 References; CHAPTER 6: DIGITAL DESIGN THROUGH VERILOG HDL; 6.1 Introduction; 6.1.1 What is Verilog HDL; 6.1.2 Backgrounnd; 6.1.3 Compiler Directives; 6.1.4 Data Types; 6.1.5 Operators; 6.2 Module and Test bench Definitions; 6.2.1 Module; 6.2.2 Test bench; 6.3 Gate-Level Modeling; 6.3.1 Built-in primitives; 6.3.2 Single and multiple input gates; 6.3.3 Tristate gates; 6.3.4 MOS Switch; 6.3.5 Gate Delays; 6.3.6 Example; 6.4 Dataflow Modeling; 6.4.1 Continuous Assignments; 6.4.2 Delays; 6.4.3 Examples: Verilog Program for Full Adder; 6.5 Behavioral Modeling; 6.5.1 Initial Statement; 6.5.2 Always Statement; 6.5.3 Procedural Assignments; 6.5.4 Conditional Statements; 6.5.5 Loop Statements; 6.5.6 Examples; 6.6 Tasks and Functions; 6.6.1 Tasks; 6.6.2 Functions; 6.7 Summary; 6.8 Multiple Choice Questions; 6.9 Short Questions; 6.10 Long Questions; 6.11 References CHAPTER 7 VLSI INTERCONNECT AND IMPLEMENTATION; 7.1 An overview of the VLSI Interconnect Problem; 7.1.1 Interconnect Scaling Problem; 7.1.2 Implementation of Interconnect Problem; 7.2 Interconnect Aware Design Methodology and Electrical Modeling; 7.2.1 Impact of Scaling; 7.2.2 Transistor Scaling; 7.2.3 Interconnect Scaling; 7.3 Electrical Circuit Model of Interconnect; 7.3.1 Ideal Interconnect; 7.3.2 Resistive Interconnect; 7.3.3 Capacitive Interconnect; 7.3.4 Resistive Interconnect Tree; 7.4 Estimation of Interconnect Parasitics; 7.4.1 Interconnect Resistance Estimation; 7.4.2 Interconnect Inductance Estimation; 7.4.3 Interconnect Capacitance Estimation; 7.4.3.1 Parallel Plate Capacitor; 7.4.3.2 Fringing Capacitance; 7.4.3.3 Lateral Capacitance; 7.5 Calculation of Interconnect Delay; 7.5.1 RC Delay Model; 7.5.2 Elmore Delay Model; 7.5.3 Transfer Function Model based on ABCD Parameter matrix; 7.5.4 Finite Difference Time Domain Model (FDTD); 7.6 Estimation of Interconnect Crosstalk Noise; 7.7 Estimation of Interconnect Power Dissipation; 7.8 Summary; 7.9 Multiple Choice Questions; 7.10 Short Answer Questions; 7.11 Long Answer Questions; 7.12 References CH
• Edition: 1st
• Publisher Details: Boca Raton : CRC Press
• Publication Date: 2020
• Extent: 1 online resource, illustrations (black and white)
• Subjects: 621.381; Microelectronics; Nanoelectronics
• Languages: English
• ISBNs: 9781000223095; 9781000223071; 9781000223088; 9781003049203
• Related ISBNs: 9780367502379
• Notes: Note: Description based on CIP data; resource not viewed.
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