Reliability enhancement of a steep slope tunnel transistor based ring oscillator designs with circuit interaction. Issue 6 (1st November 2016)

• Record Type: Journal Article
• Authors: Japa, Aditya; Vallabhaneni, Harshita; Vaddi, Ramesh
• Is Part Of: IET circuits, devices & systems. Volume 10:Issue 6(2016)
• Page Start: 522
• Page End: 527
• Publication Date: 2016-11-01
• Subjects: tunnel transistors -- oscillators -- network synthesis -- field effect transistors -- circuit reliability; reliability enhancement -- steep slope tunnel transistor -- ring oscillator design -- circuit interaction -- tunnel field effect transistors -- post-CMOS technology -- digital design -- analogue design -- RF design -- TFET circuit reliability -- on-state Miller capacitance effect -- transient characteristics -- energy efficiency -- optimal sizing -- stage number -- supply voltage -- TFET-based circuit interaction design approach -- ultralow-power ring oscillator circuit design -- ring oscillator circuit design reliability -- TFET circuit co-design approach -- differential topology-based design -- complementary static TFET logic designs; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2016.0262
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : Tunnel field effect transistors (TFETs) have emerged as one of the most promising post‐CMOS technologies for digital, analogue and RF designs. However, it has been demonstrated by several researchers that TFET circuits face increased on‐state Miller capacitance effect, which leads to poor transient characteristics with large overshoots and undershoots. This would minimise the reliability of TFET circuits though energy efficient. This work gives more design insights (optimal sizing, number of stages, supply voltage) into TFET circuit reliability and proposes a TFET based circuit interaction design approach for ultra‐low power and reliable ring oscillator circuit design. It has been shown that TFET circuit designs without proper reliability enhancement techniques such as circuit interaction or co‐design approach exhibits very large undershoots/overshoots (∼20–50%). The proposed TFET circuit co‐design approach (i.e. differential topology based design in comparison with the complementary static TFET logic designs) enhances the TFET circuit reliability by minimising the undershoots/overshoots to less than 0.5% with a trade‐off in operating frequency and power consumption.