Tunnel FET ambipolarity‐based energy efficient and robust true random number generator against reverse engineering attacks. Issue 5 (1st July 2019)

• Record Type: Journal Article
• Authors: Japa, Aditya; Majumder, Manoj Kumar; Sahoo, Subhendu K.; Vaddi, Ramesh
• Is Part Of: IET circuits, devices & systems. Volume 13:Issue 5(2019)
• Page Start: 689
• Page End: 695
• Publication Date: 2019-07-01
• Subjects: tunnel transistors -- logic gates -- field effect transistors -- oscillators -- indium compounds -- random number generation -- reverse engineering -- III-V semiconductors -- energy conservation -- logic circuits -- logic design -- failure analysis; TFET TRNG -- ambipolarity-based circuit design -- reverse engineering attacks -- robust true random number generator -- random number generator harvesting random bits -- delay variations -- TFET transmission gate functional failure -- TFET ambipolarity-based ring oscillator design -- random variations -- oscillating frequency -- TFET device ambipolarity -- TFET ambipolarity-based TRNG circuit -- tunnel FET ambipolarity-based energy efficient true random number generator -- XOR gate-based post-processing unit design -- NIST tests -- size 20.0 nm -- voltage 0.5 V -- InAs; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2018.5297
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : This study presents a true random number generator (TRNG) harvesting random bits from delay variations of ambipolarity‐based ring oscillator, designed using 20 nm InAs Tunnel FET (TFET). Exploiting the TFET transmission gate (TG) functional failure, TFET ambipolarity‐based ring oscillator design has been proposed. Random variations are observed in the oscillating frequency of proposed ring oscillator by changing the TFET device ambipolarity. Exploring the same, a TFET ambipolarity‐based TRNG circuit has been demonstrated. XOR gate‐based post‐processing unit is designed to further enhance the unpredictability and randomness of the output bits. The proposed TRNG has passed various NIST tests performed at a supply voltage of 0.5 V. In 20 nm, the proposed TFET TRNG has an area as low as 90 pm 2 and consumes 5.4 pJ/bit at 0.5 V supply voltage. Ambipolarity‐based circuit design makes the proposed TRNG robust against reverse engineering attacks.