Negative capacitance FETs for energy efficient and hardware secure logic designs. (January 2022)

• Record Type: Journal Article
• Authors: Bheemana, Renuka Chowdary; Japa, Aditya; Yellampalli, Siva Sankar; Vaddi, Ramesh
• Is Part Of: Microelectronics journal. Volume 119(2021)
• Publication Date: 2022-01
• Subjects: Negative capacitance field effect transistor (NCFET) -- Energy efficiency -- Hardware security -- Ultra low power circuit designs; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2021.105320
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: Negative capacitance field effect transistors (NCFETs) have attracted good attention for energy efficient circuit designs. However, there are no clear design insights with NCFET based circuit designs for energy efficient and hardware secure applications. However, the lack of clear design insights make energy efficient and hardware secure NCFET circuit design more challenging. This paper presents important design insights and scope of NCFETs for energy efficient and hardware secure logic design at scaled supply voltages. Initially, NCFET device characteristics have been analyzed by varying the ferroelectric layer thickness ( t fe ) to identify optimum device performance window. At 40 nm technology node, NCFET device demonstrates enhanced characteristics for logic design with t fe in the range of 3 nm–5 nm due to steep subthreshold swing characteristics. NCFET with t fe of 5 nm exhibits 1.22 × higher ON current, 66 × lower leakage current and a SS of 50mV/dec compared to baseline MOSFET ( t fe = 0 nm). Further, NCFET based static complementary inverter design exhibits better performance and higher energy efficiency compared to baseline MOSFET. NCFET inverter with t fe of 3 nm achieves optimum performance in terms of voltage transfer characteristics, differential gain, and noise margins. In addition, NCFET with t fe of 3 nm shows minimum energy consumption with the different supply voltages in the range of 0.6–0.8 V. Moreover, NCFET based buffer, logic gates and half-adder designs with t fe of 3 nm achieve approximately 3 × lower energy consumption compared to baseline designs. Apart from this, the NCFET designs exhibit 2 × higher ON current variations, 12 × higher inverter delay variations, and 3.1 × higher ring oscillator frequency variations compared to baseline designs against 5% process parameter variations at a supply voltage of 0.5 V. With the higher variations resulted from ferroelectric layer, NCFET demonstrate the potential and suitability towards the design of hardware security primitives like physically unclonable function (PUF) and true random number generator (TRNG).