Negative capacitance FET based energy efficient and DPA attack resilient ultra-light weight block cipher design. (March 2023)

• Record Type: Journal Article
• Authors: Bheemana, Renuka Chowdary; Japa, Aditya; Yellampalli, Siva sankar; Vaddi, Ramesh
• Is Part Of: Microelectronics journal. Volume 133(2023)
• Publication Date: 2023-03
• Subjects: Energy efficiency -- Negative capacitance FETs (NCFETs) -- Differential power analysis (DPA) attacks -- PRESENT-80 -- Light weight block ciphers; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2023.105711
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: Energy-efficient and secure cipher design for resource constrained IoT applications is a pressing challenge with CMOS technology scaling and increased hardware attacks. This work presents the potential and design challenges exploring Negative Capacitance FETs (NCFETs) for energy efficient and differential power analysis (DPA) attack resilient circuit/cipher design at scaled supply voltages. Design and performance benchmarking of one such ultra-light weight block cipher, i.e. PRESENT-80 exploring 40 nm NCFET device technology is demonstrated and evaluated resiliency against DPA attack for the first time. 40 nm NCFETs show optimum device performance with a ferroelectric layer thickness (tfe) in the range of 3 nm–5 nm. NCFET with tfe of 5 nm shows ∼15.7 × higher ON current, 1.77 lower leakage current and subthreshold swing of 49mV/dec compared to the baseline CMOS device. NCFET based PRESENT-80 block cipher design achieves ∼3.2 × lower energy consumption compared to the baseline equivalent 40 nm CMOS design under similar design constraints. NCFET PRESENT-80 cipher design is evaluated against DPA attack and results indicate NCFET based cipher design to be highly resilient compared to the baseline CMOS design. With the non-linearity in power traces caused by the additional capacitance of NCFET device structure, the proposed NCFET PRESENT cipher design achieves ∼4 × increased attacker effort ratio and low Signal-to-noise ratio (SNR) values compared to the equivalent baseline CMOS design.