Low area overhead DPA countermeasure exploiting tunnel transistor‐based random number generator. Issue 5 (20th July 2020)

• Record Type: Journal Article
• Authors: Japa, Aditya; Kumar Majumder, Manoj; Sahoo, Subhendu K.; Vaddi, Ramesh
• Is Part Of: IET circuits, devices & systems. Volume 14:Issue 5(2020)
• Page Start: 640
• Page End: 647
• Publication Date: 2020-07-20
• Subjects: tunnel transistors -- oscillators -- random number generation -- cryptography -- field effect transistors -- reverse engineering -- integrated circuit design -- CMOS integrated circuits; differential power analysis -- efficient side channel attack -- extracted power traces -- traditional CMOS-based DPA countermeasures -- DPA countermeasure -- negative drain-to-source voltage bias -- behaviour TFET RNG -- extracts random bits -- TFET ring oscillator -- low area overhead -- original TFET substitution box -- DPA attack -- TFET designs -- TFET transmission gate -- tunnel field effect transistors -- tunnel transistor-based random number generator; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2019.0504
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : Differential power analysis (DPA) has become an efficient side channel attack that obtains a secret key from the extracted power traces. Several traditional CMOS‐based DPA countermeasures resulted in high area overhead and performance degradation. This study presents low area overhead DPA countermeasure exploring tunnel field effect transistors (TFET) based random number generator (RNG). TFET exhibits significant p–i–n forward current with an increase in negative drain‐to‐source voltage bias. It is demonstrated that TFET transmission gate exhibits unconventional behaviour due to p–i–n forward current of the device. Leveraging this behaviour TFET RNG is designed that extracts random bits from delay variations of the TFET ring oscillator. The proposed TFET RNG achieves low area overhead when compared with the baseline CMOS designs. The proposed DPA countermeasure is demonstrated by integrating the original TFET substitution box (S‐box) and TFET RNG. The proposed architecture is found to be resilient to DPA attack and the area overhead of single S‐box and Advanced Encryption Standard AES is as low as 12 and 5%, respectively. Apart from low area overhead, the TFET designs with inherent device characteristics show high robustness against reverse engineering attacks which provide a higher level of security to TFET‐based circuits and systems.