1. A 2-D compact DC model for engineered nanowire JAM-MOSFETs valid for all operating regimes. (2nd July 2020) Authors: Baral, Kamalaksha; Singh, Prince Kr; Kumar, Sanjay; Tripathy, Manas Ranjan; Singh, Ashish Kr; Chander, Sweta; Jit, S Journal: Semiconductor science and technology Issue: Volume 35:Number 8(2020) Page Start: Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
2. Comprehensive review on electrical noise analysis of TFET structures. (January 2022) Authors: Chander, Sweta; Sinha, Sanjeet Kumar; Chaudhary, Rekha Journal: Superlattices and microstructures Issue: Volume 161(2022) Page Start: Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
3. Effect of noise components on L-shaped and T-shaped heterojunction tunnel field effect transistors. (1st July 2022) Authors: Chander, Sweta; Sinha, Sanjeet Kumar; Chaudhary, Rekha; Goswami, Rupam Journal: Semiconductor science and technology Issue: Volume 37:Number 7(2022) Page Start: Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
4. Effect of shifted gate stack engineering over negative capacitance tunnel field effect transistor (NCTFET). (1st September 2022) Authors: Singh, Amandeep; Sinha, Sanjeet Kumar; Chander, Sweta Journal: Engineering research express Issue: Volume 4:Number 3(2022) Page Start: Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
5. Heterojunction fully depleted SOI-TFET with oxide/source overlap. (October 2015) Authors: Chander, Sweta; Bhowmick, B.; Baishya, S. Journal: Superlattices and microstructures Issue: Volume 86(2015) Page Start: 43 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
6. Heterojunction fully depleted SOI-TFET with oxide/source overlap. (October 2015) Authors: Chander, Sweta; Bhowmick, B.; Baishya, S. Journal: Superlattices and microstructures Issue: Volume 86(2015) Page Start: 43 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
7. Investigation of DC performance of Ge-source pocket silicon-on-insulator tunnel field effect transistor in nano regime. (6th May 2021) Authors: Sinha, Sanjeet Kumar; Chander, Sweta Journal: International journal of nanoparticles Issue: Volume 13:Number 1(2021) Page Start: 13 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
8. Simulation Analysis of Noise Components in NCTFET with Ferroelectric Layer in Gate Stack. Issue 1 (2nd January 2023) Authors: Singh, Amandeep; Sinha, Sanjeet Kumar; Chander, Sweta Journal: Integrated ferroelectrics Issue: Volume 231:Issue 1(2023) Page Start: 171 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
9. Simulation Study of Hetero-Junction Single Gate Extended Source TFET. Issue 1 (1st August 2022) Authors: Singh, Suryavansh; Roy, Saurav Guha; Kumari, Anjali; Chander, Sweta; Sinha, Sanjeet Kumar; Chaudhary, Rekha Journal: Journal of physics Issue: Volume 2325:Issue 1(2022) Page Start: Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
10. TCAD analysis of tunnel field effect transistor using Ge material for low power application. (2022) Authors: Chander, Sweta; Chaudhary, Rekha; Sinha, Sanjeet Kumar Journal: Materials today Issue: Volume 50:Part 5(2022) Page Start: 2398 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗