A 2-D compact DC model for engineered nanowire JAM-MOSFETs valid for all operating regimes. (2nd July 2020)

• Record Type: Journal Article
• Authors: Baral, Kamalaksha; Singh, Prince Kr; Kumar, Sanjay; Tripathy, Manas Ranjan; Singh, Ashish Kr; Chander, Sweta; Jit, S
• Is Part Of: Semiconductor science and technology. Volume 35:Number 8(2020)
• Publication Date: 2020-07-02
• Subjects: junctionless accumulation mode MOSFET -- device engineering -- doped device -- quantum confinement -- continuous 2-D potential model; Semiconductors -- Periodicals; 621.38152
• DOI: 10.1088/1361-6641/ab8fc0
• Languages: English
• ISSNs: 0268-1242

Abstract

Abstract: This manuscript reports a 2-D compact analytical model for DC characteristics under all possible regimes of operations of a cylindrical gate nanowire junctionless accumulation mode MOSFET including the effects of various device engineering techniques. Superposition technique with appropriate boundary conditions has been used to solve 2-D Poisson's equation considering both free/accumulation and depletion charges. The minimum potential concept has been used to conceive the threshold voltage formulation considering the effects of structural and electrical quantum confinements. An optimized device model has been formulated incorporating various device engineering. The potential model could also be used for potential modeling of doped inversion mode MOSFETs. Complete drain current including gate induced drain leakage has been derived from the potential model. Drain current has been derived individually for different regions. Further the effects of temperature and trapped interface charges have been included in the model. A 3-D commercial TCAD has been used to validate the model results of our proposed device.