Cite
MLA Citation
A. Ahilan and P. Deepa. “Design for built-in FPGA reliability via fine-grained 2-D error correction codes.” Microelectronics and reliability, vol. 55, no. 9, 2015, pp. 2108–2112. http://access.bl.uk/ark:/81055/vdc_100051343960.0x00005f