1. Accuracy enhancement of equal segment based approximate adders. Issue 5 (10th July 2018) Authors: Dutt, Sunil; Nandi, Sukumar; Trivedi, Gaurav Journal: IET computers & digital techniques Issue: Volume 12:Issue 5(2018) Page Start: 206 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
2. An algorithm for obstacle‐avoiding clock routing tree construction with multiple TSVs on a 3D IC. Issue 2 (27th November 2018) Authors: Mondal, Khokan; Chatterjee, Subhajit; Samanta, Tuhina Journal: IET computers & digital techniques Issue: Volume 13:Issue 2(2019) Page Start: 102 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
3. Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex‐5 field‐programmable gate array. Issue 4 (15th March 2018) Authors: Olivito, Javier; Serrano, Felipe; Clemente, Juan Antonio; Mecha, Hortensia; Resano, Javier Journal: IET computers & digital techniques Issue: Volume 12:Issue 4(2018) Page Start: 150 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
4. Circuit enclaves susceptible to hardware Trojans insertion at gate‐level designs. Issue 6 (1st October 2018) Authors: Sebt, Seyed Mohammad; Patooghy, Ahmad; Beitollahi, Hakem; Kinsy, Michel Journal: IET computers & digital techniques Issue: Volume 12:Issue 6(2018) Page Start: 251 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
5. CUDA memory optimisation strategies for motion estimation. Issue 1 (6th September 2018) Authors: Sayadi, Fatma Elzahra; Chouchene, Marwa; Bahri, Haithem; Khemiri, Randa; Atri, Mohamed Journal: IET computers & digital techniques Issue: Volume 13:Issue 1(2019) Page Start: 20 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
6. Design and synthesis of improved reversible circuits using AIG‐ and MIG‐based graph data structures. Issue 1 (27th September 2018) Authors: Bandyopadhyay, Chandan; Das, Rakesh; Chattopadhyay, Anupam; Rahaman, Hafizur Journal: IET computers & digital techniques Issue: Volume 13:Issue 1(2019) Page Start: 38 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
7. Design of reliable storage and compute systems with lightweight group testing based non‐binary error correction codes. Issue 3 (19th December 2018) Authors: Bu, Lake; Karpovsky, Mark G.; Kinsy, Michel A. Journal: IET computers & digital techniques Issue: Volume 13:Issue 3(2019) Page Start: 140 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
8. Effect of NBTI stress on DSP cores used in CE devices: threat model and performance estimation. Issue 6 (3rd October 2018) Authors: Kachave, Deepak; Sengupta, Anirban; Neema, Shubha; Sri Harsha, Panugothu Journal: IET computers & digital techniques Issue: Volume 12:Issue 6(2018) Page Start: 268 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
9. Efficient digital implementation of a multi‐precision square‐root algorithm. Issue 2 (11th December 2018) Authors: Beasley, Alexander E.; Watson, Robert J.; Clarke, Christopher T. Journal: IET computers & digital techniques Issue: Volume 13:Issue 2(2019) Page Start: 110 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
10. Energy‐efficient fault tolerant technique for deflection routers in two‐dimensional mesh Network‐on‐Chips. Issue 3 (23rd February 2018) Authors: Sleeba, Simi Zerine; Jose, John; Mini, Maniyelil Govindankutty Journal: IET computers & digital techniques Issue: Volume 12:Issue 3(2018) Page Start: 69 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗