Circuit enclaves susceptible to hardware Trojans insertion at gate‐level designs. Issue 6 (1st October 2018)

• Record Type: Journal Article
• Authors: Sebt, Seyed Mohammad; Patooghy, Ahmad; Beitollahi, Hakem; Kinsy, Michel
• Is Part Of: IET computers & digital techniques. Volume 12:Issue 6(2018)
• Page Start: 251
• Page End: 257
• Publication Date: 2018-10-01
• Subjects: integrated circuit design -- probability -- invasive software -- integrated circuit reliability; design‐time HTs -- efficient net susceptibility metrics -- functional‐HT detection -- gate‐level digital designs -- controllability -- observability parameters -- HT‐test circuit -- net classifier method -- circuit nets -- gate‐level circuits -- Trust‐HUB benchmark suite -- circuit inputs -- hardware Trojan -- chip design -- functionality alteration -- reliability degradation -- secret information leakage -- HT activation signals -- detection accuracy -- HT trigger detection -- hardware Trojan insertion -- low overhead analysis -- circuit input switching probability; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2018.5108
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : A hardware Trojan (HT) is an extra circuitry inserted into a chip design with the malicious aim of functionality alteration, reliability degradation or secret information leakage. It is normally very hard to find HT activation signals since such signals are intended to activate upon occurring very rare conditions on specific nets of the infected circuit. A security engineer would have to search among thousands of gates and modules to make sure about the non‐existence of design‐time HTs in the circuit. The authors propose efficient net susceptibility metrics to significantly speedup functional‐HT detection in gate‐level digital designs. The proposed metrics perform a computationally low overhead analysis on the controllability and observability parameters of each net of the under HT‐test circuit. Then, using a proposed net classifier method, a very low percentage of circuit nets is determined as HT trigger suspicious nets. To show practicality and detection accuracy of the proposed metrics, gate‐level circuits of Trust‐HUB benchmark suite are examined by the proposed metrics. Results confirm a 100% HT trigger detection with a low false positive as compared with previous metrics. More importantly, unlike previously proposed methods, the authors detection accuracy is totally independent of the switching probability of circuit inputs.