An algorithm for obstacle‐avoiding clock routing tree construction with multiple TSVs on a 3D IC. Issue 2 (27th November 2018)
- Record Type:
- Journal Article
- Title:
- An algorithm for obstacle‐avoiding clock routing tree construction with multiple TSVs on a 3D IC. Issue 2 (27th November 2018)
- Main Title:
- An algorithm for obstacle‐avoiding clock routing tree construction with multiple TSVs on a 3D IC
- Authors:
- Mondal, Khokan
Chatterjee, Subhajit
Samanta, Tuhina - Abstract:
- Abstract : Effective clock tree design is an important factor for determining chip performance. In this study, the authors present a 3D clock tree design algorithm to enhance the speed and performance of a VLSI chip. The authors propose an algorithm to determine the performance of the clock network by optimising both the clock skew and the dynamic power consumption of the 3D IC clock tree. The authors propose an algorithm for clock tree design based on the Elmore Delay method and routes all the sinks efficiently considering the obstacles with the use of an optimum number of through‐silicon‐vias (TSVs). The proposed method starts with a segregation technique to divide the sinks into smaller zones. Subsequently, an obstacle avoiding abstract clock tree is constructed with a minimum number of TSVs and buffers. The skew and dynamic power of the tree is calculated. Consequently, the proposed method is compared with recent existing works. The experimental results so obtained are quite encouraging.
- Is Part Of:
- IET computers & digital techniques. Volume 13:Issue 2(2019)
- Journal:
- IET computers & digital techniques
- Issue:
- Volume 13:Issue 2(2019)
- Issue Display:
- Volume 13, Issue 2 (2019)
- Year:
- 2019
- Volume:
- 13
- Issue:
- 2
- Issue Sort Value:
- 2019-0013-0002-0000
- Page Start:
- 102
- Page End:
- 109
- Publication Date:
- 2018-11-27
- Subjects:
- clocks -- integrated circuit design -- trees (mathematics) -- VLSI -- buffer circuits -- three‐dimensional integrated circuits
obstacle‐avoiding clock routing tree construction -- multiple TSVs -- effective clock tree design -- chip performance -- clock network -- clock skew -- 3D IC clock tree design algorithm -- dynamic power consumption -- Elmore delay method -- through‐silicon‐vias -- obstacle avoiding abstract clock tree
Computers -- Periodicals
Digital electronics -- Periodicals
Computer engineering -- Periodicals
Computer architecture -- Periodicals
Computer organization -- Periodicals
621.39 - Journal URLs:
- http://digital-library.theiet.org/content/journals/iet-cdt ↗
http://ieeexplore.ieee.org/servlet/opac?punumber=4117424 ↗
http://www.ietdl.org/IET-CDT ↗
https://ietresearch.onlinelibrary.wiley.com/journal/1751861x ↗
http://www.theiet.org/ ↗ - DOI:
- 10.1049/iet-cdt.2018.5105 ↗
- Languages:
- English
- ISSNs:
- 1751-8601
- Deposit Type:
- Legaldeposit
- View Content:
- Available online (eLD content is only available in our Reading Rooms) ↗
- Physical Locations:
- British Library DSC - 4363.252300
British Library DSC - BLDSS-3PM
British Library HMNTS - ELD Digital store - Ingest File:
- 17121.xml