Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex‐5 field‐programmable gate array. Issue 4 (15th March 2018)

• Record Type: Journal Article
• Authors: Olivito, Javier; Serrano, Felipe; Clemente, Juan Antonio; Mecha, Hortensia; Resano, Javier
• Is Part Of: IET computers & digital techniques. Volume 12:Issue 4(2018)
• Page Start: 150
• Page End: 157
• Publication Date: 2018-03-15
• Subjects: cache storage -- field programmable gate arrays; reconfiguration latency -- energy overhead -- Xilinx Virtex‐5 field programmable gate array -- scratchpad memory -- reconfiguration controller -- reconfiguration process -- prefetching -- caching; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2016.0095
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : In this study, the authors have evaluated the overhead and the tradeoffs of a set of components usually included in a system with run‐time partial reconfiguration implemented on a Xilinx Virtex‐5. The authors' analysis shows the benefits of including a scratchpad memory inside the reconfiguration controller in order to improve the efficiency of the reconfiguration process. They have designed a simple controller for this scratchpad that includes support for prefetching and caching in order to further reduce both the energy and latency overhead.