1. A method to recover critical bits under a double error in SEC-DED protected memories. (June 2017) Authors: Liu, Shanshan; Reviriego, Pedro; Xiao, Liyi; Maestro, Juan Antonio Journal: Microelectronics and reliability Issue: Volume 73(2017) Page Start: 92 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
2. Characterizing a RISC-V SRAM-based FPGA implementation against Single Event Upsets using fault injection. (November 2017) Authors: Ramos, Alexis; Maestro, Juan Antonio; Reviriego, Pedro Journal: Microelectronics and reliability Issue: Volume 78(2017) Page Start: 205 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
3. Comments on "Extend orthogonal Latin square codes for 32-bit data protection in memory applications" Microelectron. Reliab. 63, 278–283 (2016). (February 2017) Authors: Liu, Shanshan; Reviriego, Pedro; Sánchez-Macián, Alfonso; Maestro, Juan Antonio; Xiao, Liyi Journal: Microelectronics and reliability Issue: Volume 69(2017) Page Start: 126 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
4. Efficient implementation of single event upset tolerant register comparison. Issue 23 (1st November 2016) Authors: Reviriego, Pedro; Liu, Shanshan; Xiao, Liyi; Maestro, Juan Antonio Journal: Electronics letters Issue: Volume 52:Issue 23(2016) Page Start: 1922 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
5. Fault tolerant encoders for Single Error Correction and Double Adjacent Error Correction codes. (February 2018) Authors: Liu, Shanshan; Reviriego, Pedro; Maestro, Juan Antonio; Xiao, Liyi Journal: Microelectronics and reliability Issue: Volume 81(2018) Page Start: 167 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
6. Implementing Double Error Correction Orthogonal Latin Squares Codes in SRAM-based FPGAs. (January 2016) Authors: Demirci, Mustafa; Reviriego, Pedro; Maestro, Juan Antonio Journal: Microelectronics and reliability Issue: Volume 56(2016) Page Start: 221 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
7. Implementing Double Error Correction Orthogonal Latin Squares Codes in SRAM-based FPGAs. (January 2016) Authors: Demirci, Mustafa; Reviriego, Pedro; Maestro, Juan Antonio Journal: Microelectronics and reliability Issue: Volume 56(2016) Page Start: 221 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
8. Improving Instruction TLB Reliability with Efficient Multi-bit Soft Error Protection. (February 2019) Authors: Kiani, Vahdaneh; Reviriego, Pedro Journal: Microelectronics and reliability Issue: Volume 93(2019) Page Start: 29 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
9. Low delay Single Error Correction and Double Adjacent Error Correction (SEC-DAEC) codes. (June 2019) Authors: Li, Jiaqiang; Reviriego, Pedro; Xiao, Liyi; Liu, Zhaochi; Li, Linzhe; Ullah, Anees Journal: Microelectronics and reliability Issue: Volume 97(2019) Page Start: 31 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
10. Modular fault tolerant processor architecture on a SoC for space. (April 2018) Authors: Tabero, Jesús; Regadío, Alberto; Pérez, César; Pazos, Jesús; Reviriego, Pedro; Sánchez-Macian, Alfonso; Maestro, Juan Antonio Journal: Microelectronics and reliability Issue: Volume 83(2018) Page Start: 84 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗