Characterizing a RISC-V SRAM-based FPGA implementation against Single Event Upsets using fault injection. (November 2017)

• Record Type: Journal Article
• Authors: Ramos, Alexis; Maestro, Juan Antonio; Reviriego, Pedro
• Is Part Of: Microelectronics and reliability. Volume 78(2017)
• Page Start: 205
• Page End: 211
• Publication Date: 2017-11
• Subjects: Fault injection -- Fault tolerance -- FPGA -- lowRISC -- RISC-V -- Soft core -- Soft error; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2017.09.007
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: The reliability of microprocessors is a big concern in space environments, where they are exposed to cosmic radiation. This radiation can produce Single Event Upsets (SEUs). Some of these microprocessors, often called soft processors, are implemented on SRAM-based FPGAs instead of being manufactured as an ASIC. Fault injection campaigns are needed in order to estimate the soft processor reliability in this harsh environment. This work, characterizes a new RISC soft-core, called lowRISC, based on the RISC-V ISA. Ten tests have been carried out to characterize the SEU sensitivity of lowRISC. Also, we have performed a comparison among lowRISC and other microprocessors, concluding that their sensitivities are all in the same range. Highlights: In this work, a RISC-V ISA based soft processor, lowRISC, is analysed to study its reliability. The lowRISC normalized sensitivity is compared with other microprocessors. The lowRISC sensitivity is acceptable but some modifications must be done to improve the reliability of the microprocessor.