Improving Instruction TLB Reliability with Efficient Multi-bit Soft Error Protection. (February 2019)

• Record Type: Journal Article
• Authors: Kiani, Vahdaneh; Reviriego, Pedro
• Is Part Of: Microelectronics and reliability. Volume 93(2019)
• Page Start: 29
• Page End: 38
• Publication Date: 2019-02
• Subjects: Translation Lookaside Buffer -- Fault tolerance -- Multi-bit soft error -- Error detection -- Error correction -- Reliability -- Performance; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2018.12.011
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: A Translation Lookaside Buffer (TLB) is a type of memory cache that is used to store recent translations of virtual to physical memory to reduce the access latency. Every time the processor accesses the virtual memory, it must be translated to the corresponding physical address, so the number of accesses to the TLB is high. Consequently, soft errors affecting the TLB can lead to hard fault, silent data corruption, and system freeze by corrupting its content. Many studies have proposed to provide protection for the Content Addressable Memory (CAM), which is a part of a TLB that stores the VPNs, but these protection techniques in most cases do not cover the case of multiple errors. This paper presents an efficient, fast and high error coverage approach to improve the reliability of TLB against Multiple Bit Upsets (MBUs) by considering the performance improvement with a low-cost overhead.