Implementing Double Error Correction Orthogonal Latin Squares Codes in SRAM-based FPGAs. (January 2016)

• Record Type: Journal Article
• Authors: Demirci, Mustafa; Reviriego, Pedro; Maestro, Juan Antonio
• Is Part Of: Microelectronics and reliability. Volume 56(2016)
• Page Start: 221
• Page End: 227
• Publication Date: 2016-01
• Subjects: Error Correction Codes -- FPGAs -- Orthogonal Latin Squares Codes -- Error injection testing; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2015.10.016
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: This paper studies the implementation of Double Error Correction Orthogonal Latin Squares (OLS) in Xilinx Field Programmable Gate Arrays (FPGAs). Several existing options to implement the decoder are considered and evaluated. The results show that the decoder complexity can be significantly optimized by appropriately selecting the implementation that is better suited to the internal FPGA structure. A new implementation tailored for the FPGA structure is proposed, which has a more efficient physical resource utilization compared with the existing ones. It is shown that the improvement on resource utilization is also highly correlated with the soft error vulnerability. The proposed decoder scheme has a reduced soft error cross section compared with other implementations. Based on these results, it seems that optimizing the ECC implementation for FPGAs can be effective and may be useful for other codes. Highlights: A method for optimizing ECCs for Xilinx FPGAs is proposed. Orthogonal Latin Square Codes (OLS) are taken into consideration for implementation. Synthesis and error injection testing are conducted for investigating effects of optimization.