1. A review of the Z2-FET 1T-DRAM memory: Operation mechanisms and key parameters. (May 2018) Authors: Cristoloveanu, S.; Lee, K.H.; Parihar, M.S.; El Dirani, H.; Lacord, J.; Martinie, S.; Le Royer, C.; Barbe, J.-Ch.; Mescot, X.; Fonteneau, P.; Galy, Ph.; Gamiz, F.; Navarro, C.; Cheng, B.; Duan, M.; Adamu-Lema, F.; Asenov, A.; Taur, Y.; Xu, Y.; Kim, Y-T. Journal: Solid-state electronics Issue: Volume 143(2018) Page Start: 10 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
2. Accurate statistical extraction of AlGaN/GaN HEMT device parameters using the Y-function. (October 2021) Authors: Kom Kammeugne, R.; Leroux, C.; Cluzel, J.; Vauche, L.; Le Royer, C.; Krakovinsky, A.; Gwoziecki, R.; Biscarrat, J.; Gaillard, F.; Charles, M.; Bano, E.; Ghibaudo, G. Journal: Solid-state electronics Issue: Volume 184(2021) Page Start: Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
3. Fabrication and electrical characterizations of SGOI tunnel FETs with gate length down to 50 nm. (January 2016) Authors: Le Royer, C.; Villalon, A.; Hutin, L.; Martinie, S.; Nguyen, P.; Barraud, S.; Glowacki, F.; Allain, F.; Bernier, N.; Cristoloveanu, S.; Vinet, M. Journal: Solid-state electronics Issue: Volume 115 Part B(2016) Page Start: 167 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
4. Germanium on insulator and new 3D architectures opportunities for integration. (22nd February 2010) Authors: Vinet, M.; Le Royer, C.; Batude, P.; Damlencourt, J-F.; Hartmann, J-M.; Hutin, L.; Romanjek, K.; Pouydebasque, A.; Thomas, O. Journal: International journal of nanotechnology Issue: Volume 7:Number 4/5/6/7/8(2010) Page Start: 304 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
5. Investigation of ambipolar signature in SiGeOI homojunction tunnel FETs. (January 2016) Authors: Hutin, L.; Oeflein, R.P.; Borrel, J.; Martinie, S.; Tabone, C.; Le Royer, C.; Vinet, M. Journal: Solid-state electronics Issue: Volume 115 Part B(2016) Page Start: 160 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
6. New insights on SOI Tunnel FETs with low-temperature process flow for CoolCube™ integration. (June 2018) Authors: Diaz Llorente, C.; Le Royer, C.; Batude, P.; Fenouillet-Beranger, C.; Martinie, S.; Lu, C.-M.V.; Allain, F.; Colinge, J.-P.; Cristoloveanu, S.; Ghibaudo, G.; Vinet, M. Journal: Solid-state electronics Issue: Volume 144(2018) Page Start: 78 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
7. New prospects on high on-current and steep subthreshold slope for innovative Tunnel FET architectures. (September 2019) Authors: Diaz Llorente, C.; Colinge, J.-P.; Martinie, S.; Cristoloveanu, S.; Wan, J.; Le Royer, C.; Ghibaudo, G.; Vinet, M. Journal: Solid-state electronics Issue: Volume 159(2019) Page Start: 26 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
8. On the use of a localized STRASS technique to obtain highly tensile strained Si regions in advanced FDSOI CMOS devices. Issue 10 (9th August 2016) Authors: Bonnevialle, A.; Reboh, S.; Le Royer, C.; Morand, Y.; Hartmann, J.‐M.; Rouchon, D.; Pedini, J.‐M.; Tabone, C.; Rambal, N.; Payet, A.; Plantier, C.; Boeuf, F.; Haond, M.; Claverie, A.; Vinet, M. Journal: Physica status solidi Issue: Volume 13:Issue 10-12(2016) Page Start: 740 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗