Germanium on insulator and new 3D architectures opportunities for integration. (22nd February 2010)

• Record Type: Journal Article
• Authors: Vinet, M.; Le Royer, C.; Batude, P.; Damlencourt, J-F.; Hartmann, J-M.; Hutin, L.; Romanjek, K.; Pouydebasque, A.; Thomas, O.
• Is Part Of: International journal of nanotechnology. Volume 7:Number 4/5/6/7/8(2010)
• Page Start: 304
• Page End: 319
• Publication Date: 2010-02-22
• Subjects: transistors -- GeOI -- SOI -- scaling -- 3D integration -- CMOS integration -- germanium -- electron transport -- hole mobility -- nanotechnology; 620.505
• Languages: English
• ISSNs: 1475-7435

Abstract

Ge encounters an interest revival for CMOS applications because of its high carriers mobility. GeOI pMOSFET with excellent ON currents and controlled threshold voltage have indeed been demonstrated. However the ON performance of Ge and GeOI nMOS remains well below those of Si based nMOS. Thus we propose two possible CMOS integration approaches to benefit from on one hand the excellent hole mobility in Ge and on the other hand the good electron transport properties in Si: First, the planar co-integration of SOI nMOS and GeOI pMOS by local 'Ge enrichment', and second the 3D approach with two different stacked layers sequentially processed: SOI nMOS then Ge pMOS, thanks to Ge layer transfer after SOI nMOS process, and low thermal budget of Ge MOS process. In addition, 3D monolithic integration also represents a versatile platform for advanced functions integration.