New prospects on high on-current and steep subthreshold slope for innovative Tunnel FET architectures. (September 2019)
- Record Type:
- Journal Article
- Title:
- New prospects on high on-current and steep subthreshold slope for innovative Tunnel FET architectures. (September 2019)
- Main Title:
- New prospects on high on-current and steep subthreshold slope for innovative Tunnel FET architectures
- Authors:
- Diaz Llorente, C.
Colinge, J.-P.
Martinie, S.
Cristoloveanu, S.
Wan, J.
Le Royer, C.
Ghibaudo, G.
Vinet, M. - Abstract:
- Abstract: We propose three innovative SOI Tunnel FET architectures to solve the recurrent issue of low ION and degraded subthreshold slope measured on TFETs. These are evaluated and compared with a standard TFET structure (with lateral tunneling) using the Sentaurus TCAD tool. Extending the source (anode) at the bottom of the body region generates vertical band-to-band tunneling. Moreover, reducing the vertical distance between the extension and the gate oxide (Lrt ) yields a very steep slope and higher ION compared to a device with only lateral tunneling, but only for gate lengths longer than 100 nm. Using an ultrahigh boron dopant concentration (10 21 cm −3 ) thin layer at the bottom for extremely small body thickness (TSi < 7 nm), increases ION even for small gate lengths (LG < 100 nm). The implementation of an embedded tip in the source enhances the maximum electric field at the source/channel junction, but the impact on the performance is limited because the tunneling area is not increased. Therefore, this architecture provides a performance similar to a standard TFET. TCAD simulations using SiGe with different germanium concentrations (30% and 50%) and pure germanium, instead of silicon, show an increase of the interband tunneling current when using an ultrahigh dopant concentration thin boron layer for small gate lengths (LG < 50 nm). The reduction of the tunneling current using a relatively thick channel (11–7 nm) can be compensated by using a higher germaniumAbstract: We propose three innovative SOI Tunnel FET architectures to solve the recurrent issue of low ION and degraded subthreshold slope measured on TFETs. These are evaluated and compared with a standard TFET structure (with lateral tunneling) using the Sentaurus TCAD tool. Extending the source (anode) at the bottom of the body region generates vertical band-to-band tunneling. Moreover, reducing the vertical distance between the extension and the gate oxide (Lrt ) yields a very steep slope and higher ION compared to a device with only lateral tunneling, but only for gate lengths longer than 100 nm. Using an ultrahigh boron dopant concentration (10 21 cm −3 ) thin layer at the bottom for extremely small body thickness (TSi < 7 nm), increases ION even for small gate lengths (LG < 100 nm). The implementation of an embedded tip in the source enhances the maximum electric field at the source/channel junction, but the impact on the performance is limited because the tunneling area is not increased. Therefore, this architecture provides a performance similar to a standard TFET. TCAD simulations using SiGe with different germanium concentrations (30% and 50%) and pure germanium, instead of silicon, show an increase of the interband tunneling current when using an ultrahigh dopant concentration thin boron layer for small gate lengths (LG < 50 nm). The reduction of the tunneling current using a relatively thick channel (11–7 nm) can be compensated by using a higher germanium concentration to reduce the energy bandgap. However, this will increase the density of defects causing a TAT tunneling instead of interband tunneling, jeopardizing the possibility of achieving a subthreshold swing below 60 mV/dec. … (more)
- Is Part Of:
- Solid-state electronics. Volume 159(2019)
- Journal:
- Solid-state electronics
- Issue:
- Volume 159(2019)
- Issue Display:
- Volume 159, Issue 2019 (2019)
- Year:
- 2019
- Volume:
- 159
- Issue:
- 2019
- Issue Sort Value:
- 2019-0159-2019-0000
- Page Start:
- 26
- Page End:
- 37
- Publication Date:
- 2019-09
- Subjects:
- Tunnel FET -- SOI -- Tunneling -- BTBT -- Extended-Source -- Pure Boron
Semiconductors -- Periodicals
Semiconducteurs -- Périodiques
621.38152 - Journal URLs:
- http://www.sciencedirect.com/science/journal/00381101 ↗
http://www.elsevier.com/journals ↗ - DOI:
- 10.1016/j.sse.2019.03.046 ↗
- Languages:
- English
- ISSNs:
- 0038-1101
- Deposit Type:
- Legaldeposit
- View Content:
- Available online (eLD content is only available in our Reading Rooms) ↗
- Physical Locations:
- British Library DSC - 8327.385000
British Library DSC - BLDSS-3PM
British Library HMNTS - ELD Digital store - Ingest File:
- 10860.xml