Cite
APA Citation
Jiang, D., Jin, L., Fu, L., Li, X., Chen, G., & Huo, Z. (2016). investigation of tunneling layer and inter-gate-dielectric engineered TaN floating gate memory. Integrated ferroelectrics, (169), 146–152. http://access.bl.uk/ark:/81055/vdc_100034215084.0x000003