Investigation of tunneling layer and inter-gate-dielectric engineered TaN floating gate memory. Issue 169 (12th February 2016)

• Record Type: Journal Article
• Authors: Jiang, Dandan; Jin, Lei; Fu, Liyin; Li, Xinkai; Chen, Guoxing; Huo, Zongliang
• Is Part Of: Integrated ferroelectrics. Issue 169(2016)
• Page Start: 146
• Page End: 152
• Publication Date: 2016-02-12
• Subjects: Metal floating gate memory -- high-k -- engineered barrier; Ferroelectric devices -- Periodicals; Integrated circuits -- Periodicals; 537.244805
• DOI: 10.1080/10584587.2016.1165566
• Languages: English
• ISSNs: 1058-4587

Abstract

ABSTRACT: Metal as floating gate (FG) in combination with high-k dielectrics has been seen as a possible solution to continue the scaling of NAND flash technology node beyond 2X nm. In this work, metal FG memory device with high-k engineered Inter-Gate-Dielectric (IGD) and/or tunneling layer (TL) was detailed investigated. It presents improved performance with lower operation voltage as well as faster speed, compared to control samples. Furthermore, improvement of long-term data retention is observed for the high-k engineered devices, proving that the introduction of engineered IGD and/or TL is a promising solution for further performance improvement of full metal FG memory device.