Cite
HARVARD Citation
Jiang, D. et al. (2016). Investigation of tunneling layer and inter-gate-dielectric engineered TaN floating gate memory. Integrated ferroelectrics. pp. 146-152. [Online].
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Jiang, D. et al. (2016). Investigation of tunneling layer and inter-gate-dielectric engineered TaN floating gate memory. Integrated ferroelectrics. pp. 146-152. [Online].