1. Designing positive, negative and standard gates for ternary logics using quantum dot cellular automata. (May 2020) Authors: Kamali, Seyede Fateme; Tabrizchi, Sepehr; Mohammadyan, Somaye; Rastgoo, Morteza; Navi, Keivan Journal: Computers & electrical engineering Issue: Volume 83(2020) Page Start: Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
2. High performance, variation-tolerant CNFET ternary full adder a process, voltage, and temperature variation-resilient design. (July 2019) Authors: Firouzi, Samane; Tabrizchi, Sepehr; Sharifi, Fazel; Badawy, Abdel-Hameed Journal: Computers & electrical engineering Issue: Volume 77(2019) Page Start: 205 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
3. Method for designing ternary adder cells based on CNFETs. Issue 5 (4th July 2017) Authors: Tabrizchi, Sepehr; Panahi, Atiyeh; Sharifi, Fazel; Navi, Keivan; Bagherzadeh, Nader Journal: IET circuits, devices & systems Issue: Volume 11:Issue 5(2017) Page Start: 465 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
4. Novel CNFET ternary circuit techniques for high‐performance and energy‐efficient design. Issue 2 (30th January 2019) Authors: Tabrizchi, Sepehr; Taheri, MohammadReza; Navi, Keivan; Bagherzadeh, Nader Journal: IET circuits, devices & systems Issue: Volume 13:Issue 2(2019) Page Start: 193 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗