Novel CNFET ternary circuit techniques for high‐performance and energy‐efficient design. Issue 2 (30th January 2019)

• Record Type: Journal Article
• Authors: Tabrizchi, Sepehr; Taheri, MohammadReza; Navi, Keivan; Bagherzadeh, Nader
• Is Part Of: IET circuits, devices & systems. Volume 13:Issue 2(2019)
• Page Start: 193
• Page End: 202
• Publication Date: 2019-01-30
• Subjects: ternary logic -- carbon nanotube field effect transistors -- adders -- logic gates -- logic circuits; energy-efficient design -- performance metric cost -- ternary half-adder -- ternary partial product generator -- direct transistor level implementation -- ternary structures -- high-performance design -- CNFET model -- CNFET ternary circuit techniques -- ternary arithmetic gates -- ternary logical circuit -- carbon nanotube FET -- Synopsis HSpice tool -- size 32.0 nm -- C; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2018.5036
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : Here, the authors propose a new family of ternary circuits for a general design perspective. Besides presenting an efficient ternary logical circuit approaches, the focus of this study is also about introducing techniques for reducing the performance metric cost of the proposed family. Basic ternary arithmetic gates, ternary half‐adder, and ternary partial product generator are also proposed for two different levels. First, direct transistor level implementation is considered, next a modification in the gate level implementation representing a state‐of‐the‐art approach is addressed. Carbon nanotube FET (CNFET) is considered as an appropriate technology for implementation and realisation of ternary circuits. Therefore, simulations are carried out at 32 nm CNFET model using Synopsis HSpice tool. Simulation results show the advantages of ternary structures considering the proposed method.