Method for designing ternary adder cells based on CNFETs. Issue 5 (4th July 2017)

• Record Type: Journal Article
• Authors: Tabrizchi, Sepehr; Panahi, Atiyeh; Sharifi, Fazel; Navi, Keivan; Bagherzadeh, Nader
• Is Part Of: IET circuits, devices & systems. Volume 11:Issue 5(2017)
• Page Start: 465
• Page End: 470
• Publication Date: 2017-07-04
• Subjects: adders -- carbon nanotube field effect transistors -- logic design -- multiplexing equipment; ternary adder cell -- multiple valued logic -- digital system designer -- scalable threshold voltage -- carbon nanotube field-effect transistor -- multiple-Vt circuit design -- energy-efficient method -- one-digit adder design -- ternary multiplexer -- successor cell -- predecessor cell -- HSPICE simulation -- standard CNFET technology -- power consumption -- size 32 nm -- C; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2016.0443
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : Recently multiple valued logic has attracted the attention of digital system designers. Scalable threshold voltage values of carbon nanotube field‐effect transistors (CNFETs) can easily be utilised for multiple‐ Vt circuit designs. In this study, a novel energy‐efficient method for designing one‐digit adder is proposed. The suggested design employ ternary multiplexers to select s u c c e s s o r ¯ and p r e d e c e s s o r ¯ of input trits for the output node values. This study describes the novel ternary multiplexer, s u c c e s s o r ¯ and p r e d e c e s s o r ¯ cells. The proposed full adder design is evaluated using HSPICE simulation with the standard 32 nm CNFET technology under different operational conditions, including different supply voltages, variation of output load and various operational temperatures. In addition, the sensitivity to process variations of the design is investigated. Finally, the proposed designs are compared with state‐of‐the‐art ternary circuits and based on the simulation results, the proposed full adder cell decreases the power consumption up to 2.3 times lower than the best existing techniques in the literature.