High performance, variation-tolerant CNFET ternary full adder a process, voltage, and temperature variation-resilient design. (July 2019)

• Record Type: Journal Article
• Authors: Firouzi, Samane; Tabrizchi, Sepehr; Sharifi, Fazel; Badawy, Abdel-Hameed
• Is Part Of: Computers & electrical engineering. Volume 77(2019)
• Page Start: 205
• Page End: 216
• Publication Date: 2019-07
• Subjects: CNFET -- MVL -- Ternary full adder -- Nanoelectronics; Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2019.05.018
• Languages: English
• ISSNs: 0045-7906

Abstract

Abstract: Multiple-valued logic (MVL) decreases interconnection requirement and power consumption by realizing more data transmission over an interconnection wire. This paper investigates the carbon nanotube field effect transistors (CNFETs) using in the design of a ternary full adder cell. The proposed design takes advantage of the exceptional properties of CNFETs such as setting the desired threshold voltages by adjusting the carbon nanotubes (CNTs) diameters. We use Synopsys HSPICE simulator with a 32 nm Stanford CNFET model to simulate the ternary adders. We evaluate and examine the proposed design under different operational conditions such as different supply voltages (V), and different temperatures (T). Also, we investigate the designs under process variations (P) sensitivity. The simulation results show that the proposed design reduces the delay and energy consumption by up to 3.7X and 1.2X compared to the best state-of-the-art methods while being tolerant to process, voltage and temperature (PVT) variations.