1. DC and low a frequency noise analysis of p channel gate all around vertically stacked silicon nanosheets. (August 2022) Authors: Cretu, B.; Veloso, A.; Simoen, E. Journal: Solid-state electronics Issue: Volume 194(2022) Page Start: Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
2. Detailed characterisation of Si Gate-All-Around Nanowire MOSFETs at cryogenic temperatures. (May 2018) Authors: Boudier, D.; Cretu, B.; Simoen, E.; Veloso, A.; Collaert, N. Journal: Solid-state electronics Issue: Volume 143(2018) Page Start: 27 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
3. Detailed low frequency noise assessment on GAA NW n-channel FETs. (August 2021) Authors: Cretu, B.; Bordin, A.; Simoen, E.; Hellings, G.; Linten, D.; Claeys, C. Journal: Solid-state electronics Issue: Volume 181/182(2021) Page Start: Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
4. Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs. (January 2015) Authors: Bühler, R.T.; Agopian, P.G.D.; Collaert, N.; Simoen, E.; Claeys, C.; Martino, J.A. Journal: Solid-state electronics Issue: Volume 103(2015) Page Start: 209 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
5. Electrical characterization of p-GeSn/n-Ge diodes with interface traps under dc and ac regimes. (August 2015) Authors: Baert, B.; Gupta, S.; Gencarelli, F.; Loo, R.; Simoen, E.; Nguyen, N.D. Journal: Solid-state electronics Issue: Volume 110(2015) Page Start: 65 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
6. Enhanced dynamic threshold voltage UTBB SOI nMOSFETs. (October 2015) Authors: Sasaki, K.R.A.; Manini, M.B.; Simoen, E.; Claeys, C.; Martino, J.A. Journal: Solid-state electronics Issue: Volume 112(2015) Page Start: 19 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
7. Gate dielectric material influence on DC behavior of MO(I)SHEMT devices operating up to 150 °C. (November 2021) Authors: Agopian, P.G.D.; Carmo, G.J.; Martino, J.A.; Simoen, E.; Peralagu, U.; Parvais, B.; Waldron, N.; Collaert, N. Journal: Solid-state electronics Issue: Volume 185(2021) Page Start: Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
8. Identification of Si film traps in p-channel SOI FinFETs using low temperature noise spectroscopy. (October 2015) Authors: Achour, H.; Cretu, B.; Simoen, E.; Routoure, J.-M.; Carin, R.; Benfdila, A.; Aoulaiche, M.; Claeys, C. Journal: Solid-state electronics Issue: Volume 112(2015) Page Start: 1 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
9. Impact of processing and back-gate biasing conditions on the low-frequency noise of ultra-thin buried oxide silicon-on-insulator nMOSFETs. (March 2015) Authors: Kudina, V.; Garbar, N.; Simoen, E.; Claeys, C. Journal: Solid-state electronics Issue: Volume 105(2015) Page Start: 37 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
10. Improved physics-based analysis to discriminate the flicker noise origin at very low temperature and drain voltage polarization. (September 2020) Authors: Cretu, B.; Boudier, D.; Simoen, E.; Veloso, A.; Collaert, N.; Claeys, C. Journal: Solid-state electronics Issue: Volume 171(2020) Page Start: Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗