DC and low a frequency noise analysis of p channel gate all around vertically stacked silicon nanosheets. (August 2022)

• Record Type: Journal Article
• Authors: Cretu, B.; Veloso, A.; Simoen, E.
• Is Part Of: Solid-state electronics. Volume 194(2022)
• Publication Date: 2022-08
• Subjects: Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2022.108360
• Languages: English
• ISSNs: 0038-1101

Abstract

Highlights: p-Channel GAA NS FETs presents excellent subthreshold slope and low leakage current. As drawback, important mobility variability and high access resistances are observed. The 1/f noise is completely explained in the framework of δn + δμ mechanism. In strong inversion the access resistances noise contribution dominates the 1/f noise. Abstract: DC and low frequency noise measurements are performed in p-channel gate all around (GAA) vertically stacked silicon nanosheets (NS) at room temperature. The key DC parameters such as threshold voltage, low field mobility, access resistance and subthreshold swing are estimated. Preliminary low frequency noise studies reveal that the 1/f noise may be explained in weak to moderate inversion by the carrier number fluctuation mechanism, while in strong inversion the access resistance noise prevails.