Enhanced dynamic threshold voltage UTBB SOI nMOSFETs. (October 2015)

• Record Type: Journal Article
• Authors: Sasaki, K.R.A.; Manini, M.B.; Simoen, E.; Claeys, C.; Martino, J.A.
• Is Part Of: Solid-state electronics. Volume 112(2015)
• Page Start: 19
• Page End: 23
• Publication Date: 2015-10
• Subjects: DTMOS -- UTBB -- SOI -- Back gate bias -- Electrical characterization; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2015.02.011
• Languages: English
• ISSNs: 0038-1101

Abstract

Abstract: This work aims to analyze the impact of the Ground Plane (GP) on a new generation of the dynamic threshold (DT2) operation in Ultra-thin Body and Buried Oxide (UTBB) SOI nMOSFETs. The DT2, using a short-circuit between the gate and the substrate contact, the enhanced dynamic threshold (eDT), where the substrate bias is a multiple value of the gate bias ( VB = k × VG, k = 1, 2, …, 5), and the inverse eDT (with VG = k × VB ) were compared to the conventional mode with grounded substrate. Although the improvement of the DT2 mode observed for devices with GP is lower, they presented lower short channel effects, mainly for shorter channel lengths. Regarding the direct and inverse eDT modes, a stronger dynamic threshold (DT) effect on devices with GP also results in better DC parameters such as lower subthreshold swing and higher maximum transconductance.