1. A highly linear RF mixer using gate-all-around junctionless transistor. Issue 2 (3rd April 2017) Authors: Pandey, Sunil; Sahu, Chitrakant; Singh, Jawar Journal: International journal of electronics letters Issue: Volume 5:Issue 2(2017) Page Start: 129 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
2. Device and circuit performance analysis of double gate junctionless transistors at Lg = 18 nm. Issue 3 (31st March 2014) Authors: Sahu, Chitrakant; Singh, Jawar Journal: Journal of engineering Issue: Volume 2014:Issue 3(2014) Page Start: 105 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
3. Exploration of temperature stability of linearity and RF performance metrics for PGP negative capacitance FET. (1st March 2023) Authors: Chaudhary, Shalini; Dewan, Basudha; Singh, Devenderpal; Sahu, Chitrakant; Yadav, Menka Journal: Semiconductor science and technology Issue: Volume 38:Number 3(2023) Page Start: Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
4. Impact of interface trap charges on analog/RF and linearity performances of PGP negative capacitance FET. (April 2023) Authors: Chaudhary, Shalini; Dewan, Basudha; Singh, Devenderpal; Sahu, Chitrakant; Yadav, Menka Journal: Microelectronics and reliability Issue: Volume 143(2023) Page Start: Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
5. Influence of dielectric material near tunnel junction on analog/RF and linearity figure of merits in hetero dielectric (HG) TFET: A detailed study. Issue 1 (25th September 2021) Authors: Saha, Rajesh; Sahu, Chitrakant Journal: International journal of RF and microwave computer-aided engineering Issue: Volume 32:Issue 1(2022) Page Start: n/a Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
6. Steep-subthreshold slope dual gate negative capacitance junction less FET with dead channel: TCAD approach for digital/ RF applications. (September 2022) Authors: Chaudhary, Shalini; Dewan, Basudha; Sahu, Chitrakant; Yadav, Menka Journal: Microelectronics journal Issue: Volume 127(2022) Page Start: Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
7. Temperature sensitivity analysis of dopingless charge-plasma transistor. (March 2016) Authors: Shrivastava, Vishwas; Kumar, Anup; Sahu, Chitrakant; Singh, Jawar Journal: Solid-state electronics Issue: Volume 117(2016) Page Start: 94 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
8. Temperature sensitivity analysis of dopingless charge-plasma transistor. (March 2016) Authors: Shrivastava, Vishwas; Kumar, Anup; Sahu, Chitrakant; Singh, Jawar Journal: Solid-state electronics Issue: Volume 117(2016) Page Start: 94 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
9. Virtually doped SiGe tunnel FET for enhanced sensitivity in biosensing applications. (August 2018) Authors: Shafi, Nawaz; Sahu, Chitrakant; Periasamy, C. Journal: Superlattices and microstructures Issue: Volume 120(2018) Page Start: 75 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗