1. Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmetic circuits. (February 2017) Authors: Strangio, S.; Palestri, P.; Lanuzza, M.; Esseni, D.; Crupi, F.; Selmi, L. Journal: Solid-state electronics Issue: Volume 128(2017) Page Start: 37 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
2. Digital and analog TFET circuits: Design and benchmark. (August 2018) Authors: Strangio, S.; Settino, F.; Palestri, P.; Lanuzza, M.; Crupi, F.; Esseni, D.; Selmi, L. Journal: Solid-state electronics Issue: Volume 146(2018) Page Start: 50 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
3. Gate‐level body biasing for subthreshold logic circuits: analytical modeling and design guidelines. (19th August 2014) Authors: Albano, D.; Lanuzza, M.; Taco, R.; Crupi, F. Journal: International journal of circuit theory and applications Issue: Volume 43:Number 11(2015:Nov.) Page Start: 1523 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
4. On recoverable behavior of PBTI in AlGaN/GaN MOS-HEMT. (June 2017) Authors: Acurio, E.; Crupi, F.; Magnone, P.; Trojman, L.; Meneghesso, G.; Iucolano, F. Journal: Solid-state electronics Issue: Volume 132(2017) Page Start: 49 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
5. TCAD modeling of bias temperature instabilities in SiC MOSFETs. (November 2021) Authors: Carangelo, G.; Reggiani, S.; Consentino, G.; Crupi, F.; Meneghesso, G. Journal: Solid-state electronics Issue: Volume 185(2021) Page Start: Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗