28 nm FD-SOI MEOL parasitic capacitance segmentation using electrical testing and semiconductor process modeling. (February 2023)

• Record Type: Journal Article
• Authors: Vianne, B.; Guillo-Lohan, B.; Quenette, V.; Legoix, B.; Vincent, B.
• Is Part Of: Solid-state electronics. Volume 200(2023)
• Publication Date: 2023-02
• Subjects: FD-SOI -- Capacitance extraction -- Virtual fabrication -- Sensitivity analysis; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2022.108572
• Languages: English
• ISSNs: 0038-1101

Abstract

Highlights: Parasitic capacitances of interconnects in FD-SOI devices were extracted using e-test and virtual fabrication modelling. Poly-to-contact capacitance varies between 2aF and 10aF, representing 10% to 30% of the total interconnect capacitance. Virtual fabrication modelling provides a fair estimation of parasitic capacitance in interconnects stacks. Abstract: This paper describes an extraction methodology for segmenting the different contributions to interconnect and contact driven parasitic capacitance present on a 28 nm Fully Depleted Silicon On Insulator technology. The segmentation was enabled by creating specific test structures that had been designed, processed, and electrically tested across full wafer mappings. A 3D semiconductor process model, including capacitance extraction, was subsequently built and calibrated using the statistical distribution of actual silicon data. Once fully calibrated (<3% mean deviation to actual data), the model was used to understand the sensitivity of parasitic capacitance to specific process/design parameters and to enable Design Technology Co-Optimization.