Effect of stacking fault in silicon induced by nanoindentation with MD simulation. (February 2015)

• Record Type: Journal Article
• Authors: Guo, Xiaoguang; Zhai, Changheng; Liu, Ziyuan; Zhang, Liang; Jin, Zhuji; Guo, Dongming
• Is Part Of: Materials science in semiconductor processing. Volume 30(2015:Feb.)
• Page Start: 112
• Page End: 117
• Publication Date: 2015-02
• Subjects: Stacking fault -- Molecular dynamics (MD) -- Silicon -- Nano-indentation; Semiconductors -- Periodicals; Integrated circuits -- Materials -- Periodicals; Semiconducteurs -- Périodiques; Circuits intégrés -- Matériaux -- Périodiques; Electronic journals; 621.38152
• DOI: 10.1016/j.mssp.2014.09.029
• Languages: English
• ISSNs: 1369-8001

Abstract

Abstract: A silicon model with the vacancy type stacking fault is built and used for MD nano-indentation simulation to study the different nano-processing characteristics of silicon, compared with the ideal silicon model. During the research, the load–displacement curve, the nano-hardness curve and the strain distribution figure are drawn to study the nano-mechanics properties. The coordination analysis method is introduced to visualize the motion of the silicon and study the structural phase transformations. The results show that the hardness of the model with stacking fault (8.9–9.9 GPa) is lower than the ideal model (9.6–10.4 GPa). The model with stacking fault has a large amount of plastic deformation, which eventually leads to a smaller elastic recovery. During the nano-indentation, there is a new structure β-Si forming in the perfect model. But in the stacking fault model, a large number of amorphous structures are formed. The material property of amorphous structure is unstable, which is not suitable for ultra-precision machining. Therefore, the stacking fault of interstitial type has an adverse impact on the nano-machining performance of the monocrystalline silicon.