Analytical model based estimation of line edge roughness induced VT variability in nanowire FETs. (November 2022)

• Record Type: Journal Article
• Authors: Inge, Shashank V.; Jain, Agam; Rawat, Amita; Ganguly, Udayan
• Is Part Of: Solid-state electronics. Volume 197(2022)
• Publication Date: 2022-11
• Subjects: NWFET -- Line edge roughness -- Analytical model -- mathematical model; LER Line Edge Roughness -- NWFET Nanowire Field Effect Transistor; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2022.108422
• Languages: English
• ISSNs: 0038-1101

Abstract

Highlights: An analytical model to predict threshold voltage (VT ) variability in LER infused Nanowire FET using percolation theory is presented. This model predicts VT variability 2.3× more accurately and 10× faster as compared with the earlier reported analytical model. The VT distribution predicted with this model shows excellent match with the stochastic 3D TCAD simulations. Abstract: The line edge roughness (LER) is one of the most dominant sources of variability in sub 10 nm technology node devices such as FinFET and Nanowire FET (NWFET). Earlier, analytical models of LER based threshold voltage ( V T ) variability on FinFET have been comprehensively explored. However, the analytical modeling front for NWFET is still an open challenge. Specifically, the previous FinFET inspired analysis used a cross-sectional area-equivalent circular diameter as effective diameter ( D eff ). The D eff defines the local V T for a cross-section that enables a percolation based V T estimation for the NWFET. In this work, we show that minimum local diameter ( D min ) is a better predictor. D min captures the quantum confinement locally more accurately in the highly scaled NWFETs of interest to enable accurate percolation. The model is tested for LER infused NWFET structures and shows an excellent match against the well-calibrated Sentaurus TCAD deck with the RMS error less than 1.5 mV. The model is 5 × 10 5 times computationally efficient in comparison to conventional TCAD simulations. Moreover, the proposed D min based analytical model is 2.3× better in terms of accuracy and 10× faster as opposed to the state-of-the-art (i.e. D eff based model). Such analytical models can be integrated in BSIM CMG platform to enable device scaling study and its impact on circuit level performance predictions.