A simulation-based evaluation of single-event burnout mechanisms and varied SEB hardening designs in power LDMOS transistors. (August 2022)

• Record Type: Journal Article
• Authors: Lei, Yibo; Fang, Jian; Zhang, Bo
• Is Part Of: Microelectronics and reliability. Volume 135(2022)
• Publication Date: 2022-08
• Subjects: Power LDMOS transistor -- Single-event burnout (SEB) -- SEB hardening -- Radiation response -- Technology computer-aided design (TCAD); Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2022.114598
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: In this paper, the Single-event burnout (SEB) triggering mechanism for laterally-diffused metal-oxide semiconductor (LDMOS) devices is numerically studied by using the 2D technology computer-aided design device simulator, simultaneously, three hardening designs are proposed for the first time. SEB triggering voltage (VSEB ) are extracted and compared between the four structures when the heavy ion with a same linear energy transfer (LET) of 0.2pC/μm strikes the most sensitive point of the devices. The occurrence mechanism of SEB in LDMOS is mainly due to avalanche breakdown caused by high electric field, which further triggers the parasitic BJT and eventually forms regenerative feedback. By comparing the simulation results between conventional LDMOS and proposed hardened LDMOS designs, the VSEB are 197 V of conventional LDMOS, 306 V of NB LDMOS, 291 V of NP LDMOS and 394 V of NP-BP LDMOS, and their breakdown voltage(BV) are 650 V, 606 V, 555 V and 553 V respectively. With different LET values, NB LDMOS and NP LDMOS also have better SEB performance than the conventional one. Highlights: There exists a serious risk of burn out of power LDMOS devices under SEB. The triggering mechanism of SEB in LDMOS differs from that of VDMOS which is widely studied. Parasitic NPN transistor, avalanche breakdown and secondary breakdown are discussed. Three SEB hardened designs for LDMOS is proposed to improve the performance of SEB. Different LET values for SEB hardening are discussed.