Measurement and simulation of short circuit current sharing under parallel connection: SiC MOSFETs and SiC Cascode JFETs. (November 2021)

• Record Type: Journal Article
• Authors: Wu, R.; Agbo, S.N.; Mendy, S.; Bashar, E.; Jahdi, S.; Gonzalez, Ortiz; Alatise, O.
• Is Part Of: Microelectronics and reliability. Volume 126(2021)
• Publication Date: 2021-11
• Subjects: Silicon carbide -- MOSFET -- Cascode JFET -- Short-circuit; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2021.114271
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: Short-Circuit (SC) current sharing in parallel connected SiC MOSFETs and SiC Cascode JFETs have been investigated using experimental measurements and finite element models. Device parametric variation between parallel devices contributes to uneven current sharing and reduced module robustness against SC events. Experimental measurements show that threshold voltage variation is the most critical parameter in SiC MOSFETs, more so than device switching rate and initial junction temperature. The temperature coefficient of the ON-state and saturation resistance of SiC Cascode JFETs is higher than that of the SiC MOSFETs, hence, the short-circuit energy is lower because the SC current is limited more quickly in the SiC Cascode JFETs compared to SiC MOSFETs. Also, the input silicon MOSFET in the Cascode arrangement ensures better performance regarding V TH mismatch between parallel devices under SC. This is because the threshold voltage variation is less in silicon MOSFETs compared to SiC MOSFETs. Finite element models have been used to explore the differences between SiC MOSFETs and SiC Cascode JFETs under SC conditions and to explain why JFETs are better at suppressing SC currents than MOSFETs. Highlights: The performance of parallel SiC devices under short-circuit is analysed SiC MOSFETs and SiC cascode JFETs are studied experimentally and using simulation models. The role of temperature imbalance and threshold voltage imbalance is evaluated Finite element simulations show the clear differences between the technologies.