Understanding the impact of split-gate LDMOS transistors: Analysis of performance and hot-carrier-induced degradation. (November 2021)

• Record Type: Journal Article
• Authors: Magnone, P.; Tallarico, A.N.; Pistollato, S.; Depetro, R.; Croce, G.
• Is Part Of: Solid-state electronics. Volume 185(2021)
• Publication Date: 2021-11
• Subjects: LDMOS -- Hot-carrier degradation -- Split-gate -- Reliability; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2021.108068
• Languages: English
• ISSNs: 0038-1101

Abstract

Highlights: Split-gate LDMOS structure has been investigated. Input capacitance is reduced with respect to the conventional device. The adoption of a large split-gate voltage allows reducing the on-resistance of the device. Lower values of split-gate voltage allow slightly reducing the Ron degradation due to Hot-Carrier. Abstract: In this paper a split-gate LDMOS transistor is investigated. A dedicated terminal, namely split-gate, is introduced in order to control the field plate region separately with respect to the channel region. The performances of the device, in terms of on-resistance, breakdown voltage and capacitances, are compared with those of a conventional device. The hot-carrier-induced degradation of the device is also investigated, highlighting the influence of the split-gate voltage. This work allows identifying a tradeoff between the performance and reliability of the component, which is controlled by the voltage applied to the split-gate terminal.