Compact modeling of 3D vertical junctionless gate-all-around silicon nanowire transistors towards 3D logic design. (September 2021)

• Record Type: Journal Article
• Authors: Mukherjee, Chhandak; Poittevin, Arnaud; O'Connor, Ian; Larrieu, Guilhem; Maneux, Cristell
• Is Part Of: Solid-state electronics. Volume 183(2021)
• Publication Date: 2021-09
• Subjects: Junctionless nanowire transistors -- Compact model -- High-speed logic circuit -- Heterogeneous integration; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2021.108125
• Languages: English
• ISSNs: 0038-1101

Abstract

Highlights: Compact modeling of emerging 3D vertical gate-all-around junctionless nanowire technologies. Physics-based SPICE-compatible Verilog-A compact model and extensive validation on 14 nm GAA vertical JLNTs. Preliminary conventional logic circuit simulations using JLNT compact model. Inverters with passive and active load, complementary topologies as well as ring oscillators. Conceptual perspectives for innovative 3D logic cell design for energy-efficient hardware. Abstract: To sustain transistor scaling beyond lateral 7 nm devices, gate-all-around (GAA) junctionless vertical nanowire field effect transistors (JLNT) are one of the promising alternatives. To overcome the roadblocks of logic cell design using this emerging technology, this work explores compact modeling of 3D GAA-JLNTs based on physics of junctionless transport. The model features an explicit continuous analytical form of drain current calculations adapted for a 14 nm channel junctionless nanowire transistor (JLNT) technology and has been validated against extensive characterization results on a wide range of JLNT geometry, depicting good accuracy. Finally, preliminary simulations have been explored for performance assessment of logic circuits, such as inverters with passive load, active load and complementary topologies as well as ring oscillators, designed using the developed JLNT compact model.