Efficient digit‐serial modular multiplication algorithm on FPGA. Issue 5 (17th May 2018)

• Record Type: Journal Article
• Authors: Pan, Jeng‐Shyang; Song, Pengfei; Yang, Chun‐Sheng
• Is Part Of: IET circuits, devices & systems. Volume 12:Issue 5(2018)
• Page Start: 662
• Page End: 668
• Publication Date: 2018-05-17
• Subjects: field programmable gate arrays -- cryptography -- Galois fields -- table lookup; efficient digit-serial modular multiplication algorithm -- FPGA -- cryptographic application -- DSA system -- RSA system -- ECC system -- cryptoprocessor -- Galois field -- digit-serial MM method -- variable size lookup table; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2017.0300
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : For cryptographic applications, such as DSA, RSA and ECC systems, the crypto‐processors are required to perform modular multiplication (MM) on large integers over Galois field. A new digit‐serial MM method is presented by using a variable size lookup table. The proposed modular multiplier can be designed for any digit‐size d and modulus M which only requires simple operations such as addition and shifting. Based on theoretical analysis, the efficient digit‐serial MM architecture requires the latency of O ( ⌈ n / d ⌉ + d + 2 ) clock cycles. As a result, the developed architecture can achieve less area–delay product on hardware when compared with previous designs.