Efficient digit‐serial modular multiplication algorithm on FPGA. Issue 5 (17th May 2018) - Pan, Jeng‐Shyang; Song, Pengfei; Yang, Chun‐Sheng
Abstract : For cryptographic applications, such as DSA, RSA and ECC systems, the crypto‐processors are required to perform modular multiplication (MM) on large integers over Galois field. A new digit‐serial MM method is presented by using a variable size lookup table. The proposed modular multiplier can be designed for any digit‐size d and modulus M which only requires simple operations such as addition and shifting. Based on theoretical analysis, the efficient digit‐serial MM architecture requires the latency of O ( ⌈ n / d ⌉ + d + 2 ) clock cycles. As a result, the developed architecture can achieve less area–delay product on hardware when compared with previous designs.