Area efficient non‐fractional binary‐weighted split‐capacitive‐array DAC for successive‐approximation‐register ADC. Issue 7 (2nd March 2017)

• Record Type: Journal Article
• Authors: Mao, W.; Li, Y.; Heng, C.H.; Lian, Y.
• Is Part Of: Electronics letters. Volume 53:Issue 7(2017)
• Page Start: 452
• Page End: 454
• Publication Date: 2017-03-02
• Subjects: digital‐analogue conversion -- analogue‐digital conversion -- capacitors; Walden figure‐of‐merit performance -- segmentation degree optimization -- area efficient nonfractional binary‐weighted split capacitive‐array with attenuation digital‐to‐analogue converter -- NFBWA DAC -- digital‐to‐analogue converter -- successive‐approximation‐register ADC; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2016.4043
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : An area efficient non‐fractional binary‐weighted capacitive‐array with attenuation capacitor (NFBWA) digital‐to‐analogue converter (DAC) is presented for successive‐approximation‐register ADC. Based on linearity and matching requirement, the segmentation degrees (i.e. the number of bits in each split capacitive sub‐array) are optimised to minimise the switching power and area. The proposed DAC improves the Walden figure‐of‐merit performance by 1.67 and 5.45 times, respectively, compared with that of fractional binary‐weighted capacitive‐array with attenuation capacitor (FBWA) DAC and conventional NFBWA DAC at the same unit capacitor size and linearity requirement.