Area efficient non‐fractional binary‐weighted split‐capacitive‐array DAC for successive‐approximation‐register ADC. Issue 7 (2nd March 2017) - Mao, W.; Li, Y.; Heng, C.H.; Lian, Y.
Abstract : An area efficient non‐fractional binary‐weighted capacitive‐array with attenuation capacitor (NFBWA) digital‐to‐analogue converter (DAC) is presented for successive‐approximation‐register ADC. Based on linearity and matching requirement, the segmentation degrees (i.e. the number of bits in each split capacitive sub‐array) are optimised to minimise the switching power and area. The proposed DAC improves the Walden figure‐of‐merit performance by 1.67 and 5.45 times, respectively, compared with that of fractional binary‐weighted capacitive‐array with attenuation capacitor (FBWA) DAC and conventional NFBWA DAC at the same unit capacitor size and linearity requirement.