Ionizing radiation damage in 65 nm CMOS technology: Influence of geometry, bias and temperature at ultra-high doses. (January 2021)

• Record Type: Journal Article
• Authors: Borghello, G.; Lerario, E.; Faccio, F.; Koch, H.D.; Termo, G.; Michelis, S.; Marquez, F.J.; Palomo, F.R.; Muñoz, F.
• Is Part Of: Microelectronics and reliability. Volume 116(2021)
• Publication Date: 2021-01
• Subjects: 65 nm CMOS technology total ionizing dose -- Ultra-high doses -- MOSFET reliability -- High luminosity-large hadron collider -- Spacers -- Shallow trench isolation; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2020.114016
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: We studied the radiation response of 3 different 65 CMOS planar technologies at the ultra-high doses expected to be reached in the HL-LHC, the upgraded large hadron collider of CERN. All the processes studied are sensitive to radiation and show similar degradation mechanisms and, albeit with different intensities, similar dependencies on device geometry, applied polarization and temperature. The results obtained confirmed that the performance of MOS transistors exposed to ultra-high doses is mainly affected by radiation-induced charge trapped in auxiliary oxides such as shallow trench isolation oxides and spacers. The extensive data collected has been used to develop guidelines to qualify to ultra-high doses ASICs designed in the 65 technology node. Highlights: Comparison of ultra-high-TID response of 65 nm CMOS technology from 3 manufacturers. All processes are sensitive to charge trapped in STI and spacer oxides. In all processes the degradation increases with decreasing channel width and length.