Scalability comparison between raised- and embedded-SiGe source/drain structures for Si0.55Ge0.45 implant free quantum well pFET. (April 2018)

• Record Type: Journal Article
• Authors: Yamaguchi, S.; Witters, L.; Mitard, J.; Eneman, G.; Hellings, G.; Hikavyy, A.; Loo, R.; Horiguchi, N.
• Is Part Of: Microelectronics and reliability. Volume 83(2018)
• Page Start: 157
• Page End: 161
• Publication Date: 2018-04
• Subjects: SiGe channel -- Raised source/drain -- Embedded SiGe stressor -- Epitaxy -- Quantum well; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2018.03.006
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: In this work, we have studied gate length (Lgate ) scalability of Si0.55 Ge0.45 Implant Free Quantum Well (IFQW) pFET with raised and embedded Si0.75 Ge0.25 source/drain structures. Although embedded SiGe device shows higher Idsat which can be attributed to thinner Tinv (more scavenging of High-k interfacial layer), raised SiGe device has better short channel control than embedded SiGe device thanks to shallower junction depth. Raised SiGe device can scale down Lgate by 4 nm compared to embedded SiGe device while maintaining identical Ioff . This results in superior intrinsic delay in raised SiGe device. Highlights: Scalability of Si0.55 Ge0.45 Implant Free Quantum Well (IFQW) devices with raised- and embedded SiGe S/D was studied. Embedded SiGe S/D device showed higher Idsat than raised SiGe S/D device, mainly thanks to its thinner Tinv . On the other hand, raised SiGe S/D device has shallower junctions and this resulted in shorter Lg, min . Raised SiGe S/D devices was found to have the smallest intrinsic delay among the studied devices.