Can we optimize the gate oxide quality of DRAM input/output pMOSFETs by a post-deposition treatment?. (14th December 2018)

• Record Type: Journal Article
• Authors: Simoen, E; O'Sullivan, B; Ritzenthaler, R; Dentoni-Litta, E; Schram, T; Horiguchi, N; Claeys, C
• Is Part Of: Semiconductor science and technology. Volume 34:Number 1(2019)
• Publication Date: 2018-12-14
• Subjects: low-frequency noise -- decoupled plasma nitridation -- gate oxide traps -- I/O pMOSFETs; Semiconductors -- Periodicals; 621.38152
• DOI: 10.1088/1361-6641/aaf4dc
• Languages: English
• ISSNs: 0268-1242

Abstract

Abstract: In order to improve the low-frequency noise of input/output (I/O) p-metal-oxide-semiconductor field-effect transistors (pMOSFETs) with a 5 nm SiO2 /2 nm HfO2 /5 nm TiN gate stack for DRAM applications, different post-deposition treatments have been investigated. Decoupled Plasma Nitridation with various strengths is compared with an SF6 plasma anneal. Wafers with and without an Al2 O3 cap, serving as a threshold voltage shifter have also been included in the study. It is shown that the best results, i.e. the lowest 1/ f noise magnitude, have been found for the SF6 -treated I/O pMOSFETs, reaching in the best case a value comparable with SiO2 /polycrystalline silicon reference devices.