Assessment of DC and low-frequency noise performances of triple-gate FinFETs at cryogenic temperatures. (11th November 2016)

• Record Type: Journal Article
• Authors: Cretu, B; Boudier, D; Simoen, E; Veloso, A; Collaert, N
• Is Part Of: Semiconductor science and technology. Volume 31:Number 12(2016:Dec.)
• Publication Date: 2016-11-11
• Subjects: FinFET -- very low temperature -- short-channel effects -- analog parameters -- low-frequency noise -- noise spectroscopy; Semiconductors -- Periodicals; 621.38152
• DOI: 10.1088/0268-1242/31/12/124006
• Languages: English
• ISSNs: 0268-1242

Abstract

Abstract: In this work an in-depth investigation in terms of short-channel effects, analog operation and low-frequency noise performances at very low temperature operation is given. The most important electrical parameters are investigated and it is highlighted that for our devices the downscaling to sub-10 nm technologies leads to improved drain-induced barrier lowering (DIBL) and intrinsic voltage gain. As expected, cryogenic operation leads to an amelioration of the subthreshold slope and charge sharing effect. A reduction of the threshold voltage and of the effective mobility is also observed. Discontinuities in the subthreshold slope in the drain current–gate voltage characteristics can be linked to potential non-uniformities in the channel width. It was observed that noise spectra contain 1/f and generation-recombination contributions. Low-frequency noise measurements as a function of the applied gate voltage at cryogenic operation show that the carrier number fluctuations dominate the flicker noise in weak inversion. Access resistance noise contributions were evidenced in strong inversion. The fact that devices suffer from generation-recombination noise even at 10 K operation shows that there are some active traps even at this cryogenic temperature operation. The low-frequency noise measurements as a function of temperature (10 K–70 K) are used as a non-destructive device characterization tool in order to identify traps induced during the device processing and to make a correlation between the observed traps and some technological steps.