3D modelling based comprehensive analysis of high-κ gate stack graded channel dual material trigate MOSFET *Project supported by the Ministry of Electronics and Information Technology (MEITy), Govt. of India under its Visvesvaraya PhD Scheme (PhD-MLA/4(55)/2015-16). (December 2018)

• Record Type: Journal Article
• Authors: Shora, Aadil T.; Khanday, Farooq A.
• Is Part Of: Journal of semiconductors. Volume 39:Number 12(2018:Dec.)
• Publication Date: 2018-12
• Subjects: silicon-on-nothing -- short channel effects -- dual material gate; graded channel; trigate MOSFET; 2560; Semiconductors -- Periodicals; 621.38152
• DOI: 10.1088/1674-4926/39/12/124016
• Languages: English
• ISSNs: 1674-4926

Abstract

Abstract: The evolution of the traditional metal oxide semiconductor field effect transistor (MOSFET) from planar single gate devices into 3D multiple gates has led to higher package density and high current drive. However, due to continuous scaling and as a consequent close proximity between source and drain in the nano-regime, these multigate devices have been found to suffer from performance degrading short channel effects (SCEs). In this paper, a three dimensional analytical model of a trigate MOSFET incorporating non-conventional structural techniques like silicon-on-insulator, gate and channel engineering in addition to gate oxide stack is presented. The electrostatic integrity and device capability of suppressing SCEs is investigated by deriving the potential distribution profile using the three dimensional Poisson's equation along with suitable boundary conditions. The other device parameters like threshold voltage and subthreshold swing are produced from the surface potential model. The validity of the proposed structure is established by the close agreement among the results obtained from the analytical model and simulation results.