Investigation of degradation mechanisms in low-voltage p-channel power MOSFETs under High Temperature Gate Bias stress. (September 2018)

• Record Type: Journal Article
• Authors: Magnone, P.; Barletta, G.; Magrì, A.
• Is Part Of: Microelectronics and reliability. Volume 88/90(2018)
• Page Start: 438
• Page End: 442
• Publication Date: 2018-09
• Subjects: Power MOSFET -- Bias temperature instability -- High Temperature Gate Bias; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2018.06.029
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: In this work we investigate the degradation mechanisms occurring in a p-channel trench-gate power MOSFET under High Temperature Gate Bias (HTGB) stress. The impact of negative bias temperature stress is analysed by evaluating relevant figures of merit for the considered device: threshold voltage, transconductance and on-resistance. Temperatures and gate voltages as large as 175 °C and −24 V, respectively, are adopted to accelerate the degradation in the device. Moreover, in order to investigate the origin of degradation mechanisms we analyse the interface states generation and the charge trapping processes, the impact of a switching gate voltage during the stress phase and the recovery phase after HTGB stress. Highlights: High Temperature Gate Bias (HTGB) stress leads to a degradation of VT, Ron and gm in p-channel power MOSFETs. Channel component of Ron is strongly influenced by HTGB while the drift component is only slightly affected. Build-up of oxide charges is significantly affected by the switching gate voltage conditions. VT and Ron can be recovered faster with respect to gm, because interface states are slowly recovered.